A hardware description language (HDL) is a computer-language that facilitates the documentation, design, and manufacturing of a digital system, such as an integrated circuit (IC). Implementation of the digital system may include the transformation of the digital system into a set of masks for IC manufacturing, the programming of a programmable IC such as a field programmable gate array (FPGA), or the like. Using an HDL, a user can design and specify an electronic circuit, describe the operation of the circuit, and create tests to verify operation of the circuit. An HDL includes standard, text-based expressions of the spatial and temporal structure and behavior of the electronic system being modeled. HDL syntax and semantics include explicit notations for expressing concurrency. In contrast to most high level programming languages such as C or C++, an HDL also includes an explicit notion of time such as the inclusion of clock signals, which is a primary attribute of a digital system.
Within HDL design, signals may be defined as a vector of bits. Various portions of the digital system may access a portion of the vector referred to as a “slice.” For example, different portions of the digital system may utilize different slices of the vector, where a “slice” is one or more consecutive bits of the vector and may be the entire vector. In many cases, when specifying the slice of the vector that a particular portion of the digital system is to use, the upper and lower bounds of that slice must be resolved to constants within the HDL design.
In other cases, HDL compilers may allow the upper and lower bounds of the slice to be specified dynamically. Such HDL compilers, however, implement the dynamically specified bounds of the slice as circuitry in which all possible and legal slices of the vector are made available. The circuitry is typically implemented using a multiplexer having a significant number of inputs. The number of inputs to a multiplexer used in circuitry to generate all possible and legal slices of a vector is defined by the expression n(n+1)/2, where “n” is the size of the vector in bits. As may be seen from the expression, even a small vector of 4 bits requires a relatively large circuit that utilizes a 10 input multiplexer not including the enable signals. Each of the 10 inputs to the multiplexer is a 4 bit input. In the case of a 4 bit vector, all possible and legal slices of the vector are: [3:3], [3:2], [3:1], [3:0], [2:2], [2:1], [2:0], [1:1], [1:0], and [0:0], where the first number indicates the bit position of the left boundary of the slice and the second number indicates the bit position of the right boundary of the bit position. The resulting circuitry consumes significant IC resources and IC area.